Artificial Intelligence at the Edge!
In today’s connected world, more and more data is being generated and processed locally, and now AI is expanding into new arenas including smart cities, robotics, smart retail, autonomous drones, health and safety. 2019 Innovate FPGA Design contest invites you to demonstrate your visions of how FPGAs can be used to develop smart devices at the edge using one of the following platforms: Terasic OpenVINO Starter Kit or Terasic DE10-Nano Kit. You are welcome to use Intel's FPGA AI Engine (OpenVINO/DLA) which is customizable to many different networks, or you could build your own AI engine from the ground up. This is an opportunity for you to showcase your innovation with a real-world design using FPGAs!
The InnovateFPGA is a global FPGA design contest where teams from around the world compete as they invent the future of Artificial Intelligence with Terasic and Intel. The competition is open to everyone including students, professors, makers, and industry. Sign up as a team to showcase your creativity and innovation with actual results and real-world designs now!
Stage 1 Register and Submit
Time Frame: March 20 ~ June 15 (Note: All dates and times are in local time zones)
Register as a developer. You will receive a confirmation email and a unique team ID upon registration. Once registered, choose your targeted contest platform from the two development kits (DE10-Nano Kit or OpenVINO Starter Kit) and submit your project proposal based on the kit you select to Innovate FPGA website before June 15, 2019.
Each project proposal should contain:
- High-level project description
- Block diagram
- Describe the Intel FPGA virtues demonstrated by your project.
Examples of Project Proposal:
- Deadline to submit your project proposal is June 15, 2019
Stage 2 Judging Period
Time Frame: June 16 ~ June 30
The InnovateFPGA Judging Committee includes a panel of esteemed professors and scientists who deal with all aspects of FPGAs, including Field Programmable Systems, FPGA architecture and processors.
Judge committee will select regional finalists based on the design proposals submitted by each team.
Teams who advance into the next round will receive a FREE kit (selected by each team upon registration) to develop their designs.
Community Award: Global community will cast votes online for the most innovative project proposals. The team whose proposal receives the greatest number of votes in each region will win the community award and receive a Terasic Development kit.
- Judge Selection and Community voting start from June 16 to June 30, 2019
- Regional-finalists announced on July 1, 2019
- Contest platforms sent to regional finalists: July 1, 2019
Stage 3 Develop your design!
Time Frame: July 1~ September 30
Teams develop their projects using the DE10-Nano development kit or OpenVINO Starter Kit. Developers may use Arduino shields or any other boards that interface to the two boards for their design. Utilize web resource provided by Terasic, Intel, and other sponsors for technical support as needed. Upload your completed design paper and project video before the deadline (both are required).
The Design Paper should include:
- High-level project description
- Block Diagram
- Describe the FPGA virtues demonstrated by your project
- Functional Description
- Performance metrics / goals
- Design Method
Examples of Design Paper:
The Demo Video should contain:
- Live demonstration of your design
- Description of theory & function of your design
(The maximum video length is 10 minutes)
Examples of Demo Video:
Note: English subtitle is available. Click the "subtitle" button on the youtube video to turn on English subtitles.
- The last day to submit your Design Paper and Video is September 30, 2019
Stage 4 Regional Final Selection
Time Frame: October 1 ~ October 15
The Judging Committee will select 1 winner and 2 runners-up in each region to attend the Grand Final based on teams’ design papers, video presentations, and responses to judges’ questions posted to the team project site. (More information about the award in Regional Final Round can be found on “Award” section.)
The judges will evaluate the designs based on the following criteria:
- Creativity: 10%
- Functionality: 10%
- Demonstration of FPGA virtues: 20%
- Uniqueness of algorithm/IP/software: 10%
- High device resource utilization: 10%
- Outstanding/Superior performance: 20%
- Optimization of hardware/software/appearance: 20%
- Grand finalists announced: October 16, 2019
Stage 5 Grand Final
2019 InnovateFPGA Grand Final will be held together with FPT (2019 International Conference on Field-Programmable Technology) in Tianjin, China.
Winners of the Regional Finals will be invited to present and demonstrate their projects to the judging committee, consisting of esteemed scientists, professors, and industry experts, at the Grand Final event in the FPT’19 at Tianjin, China.
(The cost of travel, meals, and lodging will be included for each of the Grand Final contestants.)
Three contestants will be selected for the following awards.
- Grand Champion
- Gold Award
- Silver Award
(More information about the award in Regional Final Round can be found on “Award” section.)
Winning designs will be promoted globally by Intel, Terasic and InnovateFPGA Sponsors.
- Grand Final in Tianjin, China from Dec 11 ~ Dec 13, 2019
(More information and categories of the Grand Final award will be announced soon.)
|Items for Submission||
- Teams can be no larger than 3 members.
- All entrants must be at least 13 years of age.
- Individuals can only be a member of one team.
- Participants (particularly students) can be supervised by a teacher/professor.
- All entries must be submitted before the announced deadline; requests for extension/belated submission will not be accepted.
- Team membership cannot change without approval. If a member of the team needs to be replaced for any reason, the team must apply for approval from the organizer.
- All designs will be based on the contest plaforms: 1. DE10-Nano kit 2. OpenVINO Starter Kit. Teams may add any other hardware (e.g. Arduino shield) as needed.
- Existing designs may be submitted, but they cannot have been submitted in a previous contest of any kind, and they must not have been sold in any form. Judges reserve the right to exclude entrants whose projects appear to be commercial products.
- Each design must be created by the participants submitting it. Designs containing open source work must clearly cite ownership and/or authorship. Designs containing third party IP must demonstrate permission for its use.
- You may make changes or enhancements to your design at any time up to the judging date. Only the most recent version of your proposal, design, or video will remain on the Innovate FPGA site and be considered by the judges.
- Teams who progress to the Regional Finals must upload their entire project source code to the Innovate FPGA GitHub. The required items include:
- Intel® Quartus® software project
- Processor source code (where appropriate):
- ARM CPU application code & driver(s)
- Linux kernel
- Nios II CPU application code
- Open source license attribution for application binary files and/or drivers developed by the team must be included. We recommend using a permissive open source license such as BSD, MIT, or Apache V2.0.
- By entering the competition, you acknowledge that you are the creator of the submitted project and allow Terasic and Innovate FPGA sponsors to use your content for marketing purposes.
- Teams must not include Terasic or sponsor logos in their designs, or imply Terasic or its sponsors have endorsed it in any way.
- If you believe a team is improperly using intellectual property developed by you, you can submit a dispute to Terasic through the Innovate FPGA website.
- Employees of Terasic and contest sponsors are not eligible to enter this contest.
Regional Final AwardAll regional finalists will receive a Certificate of Excellence when selected into regional-final.
- Gold Award (1 team): $1500, Certificates, trip to FPT’19 Tianjin Grand Final
- Silver Award (2 teams): $1200, Certificates, trip to FPT’19 Tianjin Grand Final
- Bronze Award (Up to 3 teams): $800, Certificates, Terasic Development Kit (not yet decided)
- Iron Award (Up to 3 teams): $500, Certificates, Terasic Development Kit (not yet decided)
- Award of Excellence (multiple) $200, Certificates
Grand Final Award:
- Grand Champion (1 team): $5000, Champion trophy, Champion medal, Certificates, Terasic Development Kit (not yet decided)
- Silver Award (1 team): $3500, Trophy, Silver medals, Certificates, Terasic Development Kit (not yet decided)
- Bronze Award (1 team): $2000, Trophy, Bronze medals, Certificates, Terasic Development Kit (not yet decided)
- Iron Award (3 teams): $1000, Iron medals, Certificates, Terasic Development Kit (not yet decided)
- Award of Excellence: (6 teams): Certificates, Terasic Development Kit (not yet decided)
Inherent Virtues of FPGAs
The Innovate FPGA contest is an opportunity for developers to showcase one or more of the FPGA virtues and showcase how FPGAs make processors better. Judges will give extra credit for designs that illustrate how FPGAs can boost performance of critical functions, adapt to changing system requirements, and add interfaces not native to the processor.