InnovateFPGA | Americas | How it works

About InnovateFPGA

Invent the future of embedded compute!

The Innovate Asia, Nordic, and North America contests have inspired thousands of aspiring engineers to design, create, and innovate. This year, these regional events have been combined into a single global contest – Innovate FPGA – where teams from around the world compete as they invent the future of embedded compute with Terasic and Intel. The competition is open to everyone including students, professors, makers, and industry. Teams can showcase their creativity and innovation with actual results and real-world designs.

  • Eligible teams will receive a FREE DE10-Nano development kit and get the chance to win big prizes in Finals!
  • The winner will enjoy significant industry recognition and get the opportunity to be promoted by Terasic, Intel, and Innovate FPGA sponsors!

Stage 1 Register and Submit

Register as a developer. You will receive a confirmation email and a unique team ID upon registration.
Once registered, submit your project proposal to Innovate FPGA website before December 31, 2017.

Competitors can still edit & modify your proposal during Community Voting Period.
Note: All dates and times are in local time zones

Each project proposal should contain:
  • High-level project description
  • Block diagram
  • Describe the Intel FPGA virtues demonstrated by your project.
Examples of Project Proposal:

Stage 2 Community Voting

The Innovate FPGA community will cast votes online for the best project proposals. The selected teams in each region – the ones whose proposals receive the greatest number of votes - will advance to the semi-final round, and receive a FREE Terasic DE10-Nano kit and up to three Analog Plug in Boards from Analog Devices to begin developing their project.

Important Dates:
  • Deadline to submit your project proposal is December 31, 2017
    (The number of semi-finalists in each region will be announced on January 1, 2018)
  • Community voting ends January 30, 2018
  • Regional Semi-finalists announced on January 31, 2018
First-Round Selection will begin on Jan 1, 2018!
Below is the number of teams (semi-finalists)
will be selected in first-round selection:
Americas : 18+
APJ : 25+
EMEA : 30+
Greater China : 40 +

Stage 3 Develop your design!

Teams develop their projects using the DE10-Nano development kit. Developers may use Arduino shields or any other boards that interface to the DE10-Nano board for their design. Utilize web resource provided by Terasic, Intel, and other sponsors for technical support as needed. Upload your completed design paper and project video before the deadline (both are required).

The Design Paper should include:
  • High-level project description
  • Block Diagram
  • Describe the FPGA virtues demonstrated by your project
  • Functional Description
  • Performance metrics / goals
  • Design Method
  • Conclusion
Examples of Design Paper:
The Demo Video should contain:
  • Live demonstration of your design
  • Description of theory & function of your design
    (The maximum video length is 10 minutes)
Examples of Demo Video:

Note: English subtitle is available. Click the "subtitle" button on the youtube video to turn on English subtitles.

Important Dates:
  • The last day to submit your Design Paper and Video is April 30, 2018

Stage 4 Regional Semi-Finals

The contest judge will select the top 10 teams in each region to advance to regional finals based on:
1) the Design Paper, and
2) the Project Video posted to the Innovate FPGA web site by each team.

Important Dates:
  • Regional Finalists announced on May 31, 2018

Stage 5 Regional Final

A panel of judges, appointed by Terasic, will select 1 winner and 2 runners-up in each region based on team design papers, project videos, and responses to judges’ questions posted to the team project site. The judges will evaluate the designs based on the following criteria:

Design Concept
  • Creativity: 10%
  • Functionality: 15%
  • Demonstration of FPGA virtues: 20%
Design Implementation
  • Uniqueness of algorithm/IP/software: 10%
  • Device resource utilization: 25%
Design Completeness
  • Design performance: 20%
Important Dates:
  • Grand Finalists announced on July 15, 2018
Three teams will be selected to enter the Grand Final

Stage 6 Grand Final

Winners of the Regional Finals will be invited to present and demonstrate their projects to a panel of judges, consisting of industry experts, at the Grand Final event in the United States. The travel expense will be included for each of the Grand Final contestants. (Contestants need to arrange the visa by themselves. The organizing committee is not responsible for visa-related applications.)

Winners will win amazing prizes!

Winning designs will be promoted by Intel and a special edition magazine created by Terasic.

Important Dates:
  • Grand Final in August 14-16
    (Details of Grand Final will be announced later!)





  • All semi-finalists will receive a Certificate of Excellence when selected into semi-final.

Regional Final:

  • Gold Award (1 team): $1500, Certificates, trip to US Grand Final
  • Silver Award (2 teams): $1200, Certificates, trip to US Grand Final
  • Bronze Award (Up to 3 teams): $800, Certificates, DE10-Lite Kit
  • Iron Award (Up to 3 teams):$500, Certificates, DE10-Lite Kit
  • Award of Excellence (multiple): $200, Certificates

Grand Final:

  • Grand Champion (1 team): $5000, Champion trophy, Champion medal, Certificates,
    Terasic Self-Balancing Robot Bundle x3
  • Silver Award (1 team): $3500, Trophy, Silver medals, Certificates,
    Terasic Self-Balancing Robot Bundle x3
  • Bronze Award (1 team): $2000, Trophy, Bronze medals, Certificates,
    Terasic Self-Balancing Robot Bundle x3
  • Iron Award (3 teams): $1000, Iron medals, Certificates,
    Terasic Self-Balancing Robot Bundle x1
  • Award of Excellence: (6 teams): Certificates,
    Terasic Self-Balancing Robot x1

Contest Rules

  • Cheating and voting rigging are strictly forbidden.
    Once discovered, the contestant will be disqualified to compete in the contest.
  • Teams can be no larger than 3 members.
  • All entrants must be at least 15 years of age.
  • Individuals can only be a member of one team.
  • Each team/participant can submit 1 entry to the contest.
  • Participants (particularly students) can be supervised by a teacher/professor.
  • All entries must be submitted before the announced deadline; requests for extension/belated submission will not be accepted.
  • Team membership cannot change without approval. If a member of the team needs to be replaced for any reason, the team must apply for approval from the organizer.
  • All designs will be based on the DE10-Nano kit. Teams may add any other hardware (e.g. Arduino shield) as needed.
  • Existing designs may be submitted, but they cannot have been submitted in a previous contest of any kind, and they must not have been sold in any form. Judges reserve the right to exclude entrants whose projects appear to be commercial products.
  • Each design must be created by the participants submitting it. Designs containing open source work must clearly cite ownership and/or authorship. Designs containing third party IP must demonstrate permission for its use.
  • You may make changes or enhancements to your design at any time up to the judging date. Only the most recent version of your proposal, design, or video will remain on the Innovate FPGA site and be considered by the judges.
  • Teams who progress to the Regional Finals must upload their entire project source code to the Innovate FPGA GitHub. The required items include:
  • Intel® Quartus® software project
  • Processor source code (where appropriate):
    • ARM CPU application code & driver(s)
    • Linux kernel
    • Preloader
    • Makefile
    • Nios II CPU application code
  • Open source license attribution for application binary files and/or drivers developed by the team must be included. We recommend using a permissive open source license such as BSD, MIT, or Apache V2.0.
  • By entering the competition, you acknowledge that you are the creator of the submitted project and allow Terasic and Innovate FPGA sponsors to use your content for promotional purposes.
  • Teams must not include Terasic or sponsor logos in their designs, or imply Terasic or its sponsors have endorsed it in any way.
  • If you believe a team is improperly using intellectual property developed by you, you can submit a dispute to Terasic through the Innovate FPGA website.
  • Employees of Terasic and contest sponsors are not eligible to enter this contest.

Inherent Virtues of FPGAs

The Innovate FPGA contest is an opportunity for developers to showcase one or more
of the FPGA virtues, and illustrate how FPGAs make processors better.
Judges will give extra weight to designs that demonstrate how FPGAs can:

How to demonstrate the FPGA Virtues:

Boost Performance

  • Use the FPGA to perform a task or function faster than it could be performed by the CPU.
  • Use the FPGA to off-load a task or function from the CPU leaving the processor free to perform other work.

Adapt to Changes

  • Use the FPGA to perform a task or function that is expected to change over time due to evolving standards,
    algorithmic methods, or security threats.
  • Use the FPGA to demonstrate scalability of a design over time which extends or enhances system capabilities.

Expand I/O

  • Use the FPGA to add one or more interface not native to the processor.
  • Use the FPGA to create a custom peripheral set tailored to the application.