Most of the innovations that use bioinspiration are capable of achieving high-performance in contrast with standard proposals. In this context, we propose a novel bioinspired binary adder to accelerate the latency of the binary addition at reduced cost. With this in mind, we designed a generic n-bit binary adder using VHDL hardware description language and terasic FPGAs. The simulation results have depicted that the proposed adder is faster than the LPM_ADD_SUB megafunction as n goes to infinity. Also, the simulations have demonstrated that the adder consumes less area resources than the megafunction. Since the binary addition is one of the most important operations carried out in the ALUs, this adder proposal will accelerate the digital processing of many digital applications.

Project Proposal

1. High-level project introduction and performance expectation

2. Block Diagram

3. Expected sustainability results, projected resource savings