EM002 » Successive-approximation-memory (SAM) analog-to-digital converter (ADC)
In our work we will study the possibility of replacing monolithic ADC with a combination of Comparator and DAC. Adding FPGA resources (memory, hardware multipliers, configurable logic, etc.) to the Comparator+DAC structure will allow us to obtain flexible data acquisition system for various applications.
We plan to use this technology to create Time-domain reflectometer (TDR) and Sampling Oscilloscope with an equivalent sampling rate of up to 3 GS/s.
Today, a lot of data collection systems have to deal with periodic signals. Typical examples of such devices/systems are TDR, OTDR, LiDAR and so on. Also, during various physical experiments, impulsive effects on the system under study are often used, followed by the measurement of the response of its various parameters. For example, measuring the temporal characteristics of luminescence/photoluminescence in pulsed excitation.
This work is a variation of single-bit ADC. At this specific moment, the comparator outputs 1-bit of information comparing the signal under test with the DAC signal. But in contrast to the classical SAR ADC, we do not try to implement a full digitization algorithm until the next analog signal sampling. The data obtained from the comparator is stored in memory and is used in the next step when the next synchronization pulse arrives. So, in the ideal case, to digitize a signal with an 8-bit resolution we will need to process 8 periods of the signal. Visualization of the algorithm is shown in Fig.1.1
Fig. 1.1 ( Octave script available on https://pastebin.com/j40aNymz )
In our previous work, we managed to implement a fairly simple and effective method of registration of Fresnel Reflection. But without Rayleigh Scattering registration the possibilities of the device remain pretty limited. To a certain extent, this work is aimed at eliminating this disadvantage.
We would like to note the wonderful article "Comparator/DAC Combinations Solve Data-Acquisition Problems". Many problems and their elegant engineering solutions have been announced long ago.
To test the above concept we applied a widely used board containing Cyclone II FPGAs. On which the LVDS inputs of the FPGA were utilized as comparators. DAC is built according to the simplest R2R scheme. To display the information, the VGA output is used as the least time-consuming in its implementation.
Fig. 2.1 Proof of Concept
During the implementation, we intentionally went for a number of simplifications:
- tracking ADC algorithm is used;
- the actual frequency of the comparator was 625 MS/s, after deserialization the algorithm processes and displays only 1/4 of all data;
- data on VGA is displayed as it is, without averaging and scaling, with a fixed horizontal scan frequency;
- simplified synchronization scheme implemented;
- fixed compensation for output ports and DAC delays.
Fig. 2.3 - The frequency of the investigated signal (9.28MHz) is considerably less than the frequency of the DAC.
Fig. 2.4 - Frequency of the investigated signal (148.5MHz) is comparable with the DAC frequency, but less than the comparator frequency. Fig. 2.6 shows the operation in this mode.
Fig. 2.3 Square wave input - 9.28MHz
Fig. 2.4 Square wave input - 148.5MHz
Fig. 2.5 ( Octave script available on https://pastebin.com/kRK6UebK )
At the initial stage, we plan to use DAC (AD9767) installed on Terasic THDB-ADA board.
1) Highspeed AD/DA Card - THDB-ADA
- Dual DA channels with 14-bit resolution and data rate up to 125 MSPS.
It also requires minor changes to the circuit board.
It is also planned to manufacture a subsidiary board containing VIDEO DAC.
2) 10-BIT 240-MSPS VIDEO DAC - THS8135 (THS8136)
- 240-MSPS Operation;
- Generic Triple DAC Mode for Non-Video Applications.
As comparators, we plan to install a Limiting Amplifier, which is used to create SFP/XFP modules. The main advantages of it are:
- up to 10Gbps;
- 50-150 ps rise/fall times;
- 3-6 mV p-p differential input sensitivity;
- low cost, available in single quantities.
You can find a lot of documents devoted to the creation of fully digital ADC. Usually, the authors of the works are focused on the creation of general-purpose ADC, real-time ADC.
The main algorithms used:
- Sigma-Delta ADC;
- TDC based ADC.
As a result, ADC performance is limited to MS/s, in the case of Sigma-Delta ADC or require special tricks to implement TDC of high digit capacity.
In the case of repetitive signals, we have an opportunity to simplify the analog part as much as possible, transferring all the algorithms of work in the FPGA. Using the OpenVINO Starter Kit, it is possible to get easy access to high-speed FPGA ports:
- 2x40 GPIO Header
- Support 8 pairs LVDS TX and 8 pairs LVDS RX
- Configurable I/O standards: 1.5/1.8/2.5/3.3V
- Four Rx/Tx 3.125G Transceivers
- One Transceivers Block Clock
Which will be used to generate the probing signal for the TDR, as well as input signals from comparators. This feature of the OpenVINO board differs from previous developments, in which HSMC connectors were usually used to access the high-speed periphery of the FPGA.
It should be noted that the signals under study, as a rule, are not completely random. Therefore, in the implementation of TDR, we plan to use the methodology of Compressed sensing, which will allow restoring analog signals with greater accuracy and in less time.
Fig. 5.1 TimeDelay
Fig. 5.2 (L) - dV~20mV. (R) - dV~20mV, zoom (delay: word=5, bit=8)
Fig. 5.3 (L) - dV~50uV. (R) - dV~50uV, 20-point smoothed
Fig. 5.4 (L) - dV=0uV. (R) - dV=0uV, 20-point smoothed
Fig. 5.5 dV=0V, zoom
 Comparator/DAC Combinations Solve Data-Acquisition Problems
 TDC based ADC
 Compressed sensing
 Random Interleaved Sampling (RIS). LeCroy.
 Sampling Oscilloscope Questions and Answers. Pico Technology.
 MAX3747A/MAX3747B 155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers
 ADCMP580 Ultrafast SiGe Voltage Comparators