Annual: 2019

EM002 »
Successive-approximation-memory (SAM) analog-to-digital converter (ADC)
📁Digital Design
👤Daryna Dyka
 (National University of Kyiv)
📅Oct 04, 2019
Regional Final


👀 1058   💬 10

EM002 » Successive-approximation-memory (SAM) analog-to-digital converter (ADC)


In our work we will study the possibility of replacing monolithic ADC with a combination of Comparator and DAC. Adding FPGA resources (memory, hardware multipliers, configurable logic, etc.) to the Comparator+DAC structure will allow us to obtain flexible data acquisition system for various applications.
We plan to use this technology to create Time-domain reflectometer (TDR) and Sampling Oscilloscope with an equivalent sampling rate of up to 3 GS/s.

Project Proposal

1. High-level Project Description

    Today, a lot of data collection systems have to deal with periodic signals. Typical examples of such devices/systems are TDR, OTDR, LiDAR and so on. Also, during various physical experiments, impulsive effects on the system under study are often used, followed by the measurement of the response of its various parameters. For example, measuring the temporal characteristics of luminescence/photoluminescence in pulsed excitation.

    This work is a variation of single-bit ADC. At this specific moment, the comparator outputs 1-bit of information comparing the signal under test with the DAC signal. But in contrast to the classical SAR ADC, we do not try to implement a full digitization algorithm until the next analog signal sampling. The data obtained from the comparator is stored in memory and is used in the next step when the next synchronization pulse arrives. So, in the ideal case, to digitize a signal with an 8-bit resolution we will need to process 8 periods of the signal. Visualization of the algorithm is shown in Fig.1.1

Fig. 1.1 ( Octave script available on )

    In our previous work, we managed to implement a fairly simple and effective method of registration of Fresnel Reflection. But without Rayleigh Scattering registration the possibilities of the device remain pretty limited. To a certain extent, this work is aimed at eliminating this disadvantage.

    We would like to note the wonderful article "Comparator/DAC Combinations Solve Data-Acquisition Problems". Many problems and their elegant engineering solutions have been announced long ago.

2. Block Diagram

2.1 Proof of Concept. Block Diagram

    To test the above concept we applied a widely used board containing Cyclone II FPGAs. On which the LVDS inputs of the FPGA were utilized as comparators. DAC is built according to the simplest R2R scheme. To display the information, the VGA output is used as the least time-consuming in its implementation.

Fig. 2.1 Proof of Concept

    During the implementation, we intentionally went for a number of simplifications:
     - tracking ADC algorithm is used;
     - the actual frequency of the comparator was 625 MS/s, after deserialization the algorithm processes and displays only 1/4 of all data;
     - data on VGA is displayed as it is, without averaging and scaling, with a fixed horizontal scan frequency;
     - simplified synchronization scheme implemented;
     - fixed compensation for output ports and DAC delays.

Fig. 2.2

    Preliminary results
Fig. 2.3 - The frequency of the investigated signal (9.28MHz) is considerably less than the frequency of the DAC. 
Fig. 2.4 - Frequency of the investigated signal (148.5MHz) is comparable with the DAC frequency, but less than the comparator frequency. Fig. 2.6  shows the operation in this mode.

Fig. 2.3 Square wave input - 9.28MHz

Fig. 2.4 Square wave input - 148.5MHz


Fig. 2.5 ( Octave script available on )

2.2 Project Proposal. Block Diagram

Fig. 2.6

Main components
At the initial stage, we plan to use DAC (AD9767) installed on Terasic THDB-ADA board.
1) Highspeed AD/DA Card - THDB-ADA
     - Dual DA channels with 14-bit resolution and data rate up to 125 MSPS.
It also requires minor changes to the circuit board.

It is also planned to manufacture a subsidiary board containing VIDEO DAC.
2) 10-BIT 240-MSPS VIDEO DAC - THS8135 (THS8136)
     - 240-MSPS Operation;
     - Generic Triple DAC Mode for Non-Video Applications.

    The comparator:
As comparators, we plan to install a Limiting Amplifier, which is used to create SFP/XFP modules. The main advantages of it are:
     - up to 10Gbps;
     - 50-150 ps rise/fall times;
     - 3-6 mV p-p differential input sensitivity;
     - low cost, available in single quantities.

3. Intel FPGA Virtues in Your Project

    You can find a lot of documents devoted to the creation of fully digital ADC. Usually, the authors of the works are focused on the creation of general-purpose ADC, real-time ADC. 
The main algorithms used:
 - Sigma-Delta ADC;
 - TDC based ADC.
    As a result, ADC performance is limited to MS/s, in the case of Sigma-Delta ADC or require special tricks to implement TDC of high digit capacity.

    In the case of repetitive signals, we have an opportunity to simplify the analog part as much as possible, transferring all the algorithms of work in the FPGA. Using the OpenVINO Starter Kit, it is possible to get easy access to high-speed FPGA ports:
 - 2x40 GPIO Header
     - Support 8 pairs LVDS TX and 8 pairs LVDS RX
     - Configurable I/O standards: 1.5/1.8/2.5/3.3V
 - PCIe
     - Four Rx/Tx 3.125G Transceivers
     - One Transceivers Block Clock
Which will be used to generate the probing signal for the TDR, as well as input signals from comparators. This feature of the OpenVINO board differs from previous developments, in which HSMC connectors were usually used to access the high-speed periphery of the FPGA.

    It should be noted that the signals under study, as a rule, are not completely random. Therefore, in the implementation of TDR, we plan to use the methodology of Compressed sensing, which will allow restoring analog signals with greater accuracy and in less time.

4. Design Introduction


Fig.4.1 DataFlow


5. Function Description


Fig. 5.1 TimeDelay

Fig. 5.2 (L) - dV~20mV. (R) - dV~20mV, zoom (delay: word=5, bit=8)


Fig. 5.3 (L) - dV~50uV. (R) - dV~50uV, 20-point smoothed


Fig. 5.4 (L) - dV=0uV. (R) - dV=0uV, 20-point smoothed

Fig. 5.5 dV=0V, zoom


6. Performance Parameters

7. Design Architecture



[1] Comparator/DAC Combinations Solve Data-Acquisition Problems

[2] TDC based ADC

[3] Compressed sensing

[4] Random Interleaved Sampling (RIS). LeCroy.

[5] Sampling Oscilloscope Questions and Answers. Pico Technology.

[6] MAX3747A/MAX3747B 155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers

[7] ADCMP580 Ultrafast SiGe Voltage Comparators


Aleksandr Amerikanov
I saw your project and voted for it last year. How much progress have you made?
🕒 Jul 03, 2019 04:58 PM
Last summer, we accidentally found the article:
ASIC-enabled High Resolution Optical Time Domain Reflectometer
And we realized that our project largely repeats the results obtained in it. It is quite easy to increase the spatial resolution for registering Fresnel Reflection. But without Rayleigh Scattering registration the possibilities of the device remain pretty limited.
We need new crazy ideas. :-)

And we also engaged in reverse engineering "DiCon GP700" (can be found on eBay for very reasonable money). Optical switches and attenuators are now available to automate measurements.
But the most interesting thing here:

This year, students of the Higher School of Economics decided to publish all bachelor's thesis here?
🕒 Jul 03, 2019 08:36 PM
Learn to use what you have got, and you won't need what you have not.
Around the World in Eighty Days (1972 TV series)
🕒 Jul 05, 2019 10:07 AM
Aleksandr Amerikanov
Higher School of Economics (HSE Tikhonov Moscow Institute of Electronics and Mathematics) is now implementing the concept of project-based learning and building a fairly powerful project laboratories. Therefore, many students had the opportunity to implement their ideas into practice.
As far as I know, for example, this project is generally done by the FIRST-year student herself: ))
And this: - students of the THIRD-year.

I'm afraid to imagine what will be in their bachelor's thesis))
🕒 Jul 06, 2019 03:01 PM
Aleksandr Amerikanov
Вообще жаль, что русскоязычное сообщество не такое активное, что не поддерживает проекты своих коллег.
Да и вообще наших проектов мало. В прошлом году был сильный проект от КПИ, теперь, что-то не вижу.

А еще в голосовалке выходит в топ вообще что-то странное с явными признаками накрутки.
🕒 Jul 06, 2019 03:08 PM
В прошлом году был сильный проект от
и команды, несколько "проходных", типа нашего, чисто от студентов.
Похоже что сейчас Евгений больше занят проектами
+ у нас сейчас трудно оставаться вне политики... жизнь это не только FPGA.

Реальные накрутки, в нашем регионе, начнутся завтра :-)
Можно будет организовать тотализатор. Но "приз" от накруток получит только одна команда в каждом регионе. Выдержка из правил этого года:
"Judge committee will select regional finalists based on the design proposals submitted by each team.

Teams who advance into the next round will receive a FREE kit (selected by each team upon registration) to develop their designs.

Community Award: Global community will cast votes online for the most innovative project proposals. The team whose proposal receives the greatest number of votes in each region will win the community award and receive a Terasic Development kit."

Хотя "разумное" количество, накрученных голосов, может оказать нужное воздействие на Judge committee :-)
🕒 Jul 06, 2019 04:11 PM
Aleksandr Amerikanov
Ну накрутки происходят уже не первый год, с того момента, как конкурс перешел на новую платформу. Видимо Judge committee все устраивает.
Наш коллектив желает вам успеха, и счастливо пережить ці політичні перегони)), чтобы наконец все наладилось.
🕒 Jul 06, 2019 05:00 PM
Хм, странно, особых накруток голосов, не увидели. Многие команды просят проголосовать за них на всяких профильных и не очень форумах(типа поддержи национальную команду), но это не запрещено... Панчул как всегда пиарит MIPS :-)

Кстати, профильные топики на reddit крайне занятная штука. Получили интереснейший фидбек
Сейчас вникаем...
🕒 Jul 06, 2019 07:00 PM
Bing Xia
In your block diagram, I didn't see THDB-ADA card, and no DE10-nano or OpenVINO Starter Kit main board, am I right? You will port this design to them?
🕒 Jun 28, 2019 07:01 AM
Thank you for reviewing our project!
We made some changes to our block diagram on figure 2.7. We hope, that it became more understandable.
We used the board with Cyclone II just to test our concept, now we are working on the design for Cyclone V GX. However, if our project don`t make it to Stage 2, we will use Cyclone V GX Starter Kit.
Thank you!
🕒 Jun 29, 2019 05:41 PM

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