Annual: 2019

EM028 »
NoC-based multiprocessing system prototype
📁High Performance Computing
👤Andrey Zavyalov
 (National Research University Higher School of Economics)
📅Jul 06, 2019

👀 3746   💬 17

EM028 » NoC-based multiprocessing system prototype


The project is a prototype network-on-chip (NoC) based on the simple soft-processor cores schoolMIPS using FPGAs. Processing cores generate packets and transfer them among themselves; statistics of network operation is collected. The proposed system will allow of easy changing the network configuration (such parameters as the type of topology, size of buffers, traffic profile, and so on). By performing software-hardware cosimulation, the hardware prototype will increase the speed of NoC simulation hundreds of times in comparison with software-based HDL modeling.

Project Proposal

1. High-level Project Description

Development of high-performance computing systems is extremely important. One of the promising areas is the increase in the number of cores placed on the chip. The NoC allows of effective connecting more than a hundred cores of various types without loss of performance. The NoC is a way to connect IP cores using routers interconnected in a specific sequence. Data between them is transmitted in the form of packets. The development of such systems requires modeling and debugging;  however, HDL modeling allows simulating no more than 100 cores in a reasonable period of time. Therefore, such a prototype would make it possible to debug large-sized NoCs, increasing the load on them.

The project objective is to create a prototype computing system based on the NoC.

OpenVino Starter Kit was chosen for prototyping because it contains Cyclone V 5CGXFC9D6F27C7 chip with 113560 ALMs and 12492800 block memory bits, that can be enough for synthesizing large NoCs with hundreds of nodes.

As a computational core, we use a simple version of the MIPSfpga soft-processor core [1] called schoolMIPS [2, 3]. It is simply modified and takes up few space on the chip (137 ALMs on the OpenVino Starter Kit, 0.12% of resources), and it is energy efficient. To connect to the router, one needs to develop a special interface that allows of transferring data between the processing cores.

A single-buffer router [4] is used. It occupies 775 ALMs on the OpenVino Starter Kit (0.68%) using the routing table; however, it is possible to add packet routing based on internal logic to reduce the cost of memory blocks.

For connections between routers, a connection module that generates them by parameters is created. Torus, mesh, and circulant topologies [5] are available.

All the core interfaces are connected to a debugging module that counts the number of packets sent and received by the core; after that, this module sends the data to the HPS for further processing. After the network ends using the UART interface, the data file will be transferred to the PC.

There were 2 experiments for revealing dependecies of minimal packet injection delay and mean flit receive time on nodes number. For experiments used ring circulants C(n; 1, S1).


Fig. 1 - Experimental Resuts 1

Fig. 2 - Experimental Resuts 2

After NoC working end on FPGA an HPS-core will send statistics to a host PC for comparing with modeling results and analysing.

It is planned to create a real task for executing on NoC after its testing and optimization.

2. Block Diagram

SchoolMIPS Diagram [4]

Router Diagram

Topology examples

Complete prototype diagram

3. Intel FPGA Virtues in Your Project

The FPGA allows of repeated prototyping NoCs with different configurations, so they can be debugged, and the most effective ones can be identified. Using FPGA instead of HDL-model allows of increasing in the number of cores and loading the network to test its working capacity and to count its performance. By using HPS, it is possible to make a prototype autonomous and calculate work statistics directly on it in a high-level language. The results are conveniently generated and sent to a PC via UART/PCIe to obtain cosimulation venues by comparing golden and reference models execution. HPS instead of NIOS II does not occupy additional resources on the FPGA, so they can be spent on NoC increasing.


  1. S.L. Harris, D.M. Harris, D. Chaver, R. Owen, Z.L. Kakakhel, E. Sedano, Y. Panchul, B. Ableidinger, MIPSfpga: using a commercial MIPS soft-core in computer architecture education, IET Circuits, Devices Syst. 11 (2017) 283–291. doi:10.1049/iet-cds.2016.0383.

  2. D. Harris, S. Harris, Digital design and computer architecture, 2012. doi:10.1016/B978-0-12-800056-4.00022-4.


  4. A.E. Ryazanova, A.A. Amerikanov, E. V Lezhnev, Development of multiprocessor system-on-chip based on soft processor cores schoolMIPS, J. Phys. Conf. Ser. 1163 (2019) 012026. doi:10.1088/1742-6596/1163/1/012026.

  5. A.Y. Romanov, Development of routing algorithms in networks-on-chip based on ring circulant topologies, Heliyon. 5 (2019) e01516. doi:10.1016/J.HELIYON.2019.E01516.


Ievgen Korotkyi
For now there are dozen implementations for Networks-on-chip with different topologies and architectures, described via all popular languages (Verilog, VHDL, Bluespec SV, SystemC). Here only a little part of mentioned open source projects:

What innovative design or application you plan to implement for the contest?
🕒 Jul 09, 2019 09:21 PM
Korben Dallas
Very interesting. I will look for this project.
Can you explain why did you choose schoolMIPS as processing core in your work?
Good luck to you!
🕒 Jul 04, 2019 10:33 PM
Thanks for your interest. schoolMIPS was chosen because it is simple to add new commands and blocks to it and I have an experience how to do that. Also it is easy to implement such soft-processing cores on FPGA. But maybe in future there will be other processing cores or it will be possible to combine them.
🕒 Jul 05, 2019 12:57 PM
Timofei Cherkasov
My favorite project among all, Good luck!
🕒 Jul 04, 2019 03:05 PM
Thank you!) I'll try my best.
🕒 Jul 05, 2019 12:58 PM
Bilal Zafar
Very good project. Looking forward to seeing the final report and hopefully a code repository as well. Can use it in my class on microprocessors.
🕒 Jul 04, 2019 04:42 AM
Thank you for your attention. I will publish all results on GitHub after contest finishing. But how do you want to use it on microprocessors, if this project is for using on FPGA?
🕒 Jul 05, 2019 01:09 PM
Alexander Samsonov
There are some successful IC companies who started from similar projects like Calxeda. I belive it will be successful too!
🕒 Jul 04, 2019 02:09 AM
I greatly appreciate your words. Maybe in future some company will be created from this project) Or, at least, it will become commercial
🕒 Jul 05, 2019 01:13 PM
Alexander Samsonov
We produce custom FPGA boards based on CycloneV. May be in future you can contact us. An example is shown in my profile . Our company web site: is temporary unavailaable now
🕒 Jul 05, 2019 02:01 PM
Fascinating project! Go on, and it can escalate into a production stage.
🕒 Jul 01, 2019 06:23 PM
Thank you! I'll do everything possible for that.
🕒 Jul 05, 2019 01:15 PM
Alina Fedotova
Very interesting project! I'd like to work with you on a related project.
🕒 Jul 01, 2019 10:37 AM
Thanks! I expect that next group project will be productive.
🕒 Jul 01, 2019 12:33 PM
Doreen Liu
By the way, we have released openvino 2019 R1 package for OSK, you can get the package from this link:
🕒 Jun 27, 2019 02:07 PM
Doreen Liu
An excellent design.
Looking forward to your work!
🕒 Jun 27, 2019 02:07 PM
Thank you a lot! I will hard work for implementation.
🕒 Jul 01, 2019 12:28 PM

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