EM028 » NoC-based multiprocessing system prototype
The project is a prototype network-on-chip (NoC) based on the simple soft-processor cores schoolMIPS using FPGAs. Processing cores generate packets and transfer them among themselves; statistics of network operation is collected. The proposed system will allow of easy changing the network configuration (such parameters as the type of topology, size of buffers, traffic profile, and so on). By performing software-hardware cosimulation, the hardware prototype will increase the speed of NoC simulation hundreds of times in comparison with software-based HDL modeling.
Development of high-performance computing systems is extremely important. One of the promising areas is the increase in the number of cores placed on the chip. The NoC allows of effective connecting more than a hundred cores of various types without loss of performance. The NoC is a way to connect IP cores using routers interconnected in a specific sequence. Data between them is transmitted in the form of packets. The development of such systems requires modeling and debugging; however, HDL modeling allows simulating no more than 100 cores in a reasonable period of time. Therefore, such a prototype would make it possible to debug large-sized NoCs, increasing the load on them.
The project objective is to create a prototype computing system based on the NoC.
OpenVino Starter Kit was chosen for prototyping because it contains Cyclone V 5CGXFC9D6F27C7 chip with 113560 ALMs and 12492800 block memory bits, that can be enough for synthesizing large NoCs with hundreds of nodes.
As a computational core, we use a simple version of the MIPSfpga soft-processor core  called schoolMIPS [2, 3]. It is simply modified and takes up few space on the chip (137 ALMs on the OpenVino Starter Kit, 0.12% of resources), and it is energy efficient. To connect to the router, one needs to develop a special interface that allows of transferring data between the processing cores.
A single-buffer router  is used. It occupies 775 ALMs on the OpenVino Starter Kit (0.68%) using the routing table; however, it is possible to add packet routing based on internal logic to reduce the cost of memory blocks.
For connections between routers, a connection module that generates them by parameters is created. Torus, mesh, and circulant topologies  are available.
All the core interfaces are connected to a debugging module that counts the number of packets sent and received by the core; after that, this module sends the data to the HPS for further processing. After the network ends using the UART interface, the data file will be transferred to the PC.
There were 2 experiments for revealing dependecies of minimal packet injection delay and mean flit receive time on nodes number. For experiments used ring circulants C(n; 1, S1).
Fig. 1 - Experimental Resuts 1
Fig. 2 - Experimental Resuts 2
After NoC working end on FPGA an HPS-core will send statistics to a host PC for comparing with modeling results and analysing.
It is planned to create a real task for executing on NoC after its testing and optimization.
SchoolMIPS Diagram 
Complete prototype diagram
The FPGA allows of repeated prototyping NoCs with different configurations, so they can be debugged, and the most effective ones can be identified. Using FPGA instead of HDL-model allows of increasing in the number of cores and loading the network to test its working capacity and to count its performance. By using HPS, it is possible to make a prototype autonomous and calculate work statistics directly on it in a high-level language. The results are conveniently generated and sent to a PC via UART/PCIe to obtain cosimulation venues by comparing golden and reference models execution. HPS instead of NIOS II does not occupy additional resources on the FPGA, so they can be spent on NoC increasing.
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A.E. Ryazanova, A.A. Amerikanov, E. V Lezhnev, Development of multiprocessor system-on-chip based on soft processor cores schoolMIPS, J. Phys. Conf. Ser. 1163 (2019) 012026. doi:10.1088/1742-6596/1163/1/012026.
A.Y. Romanov, Development of routing algorithms in networks-on-chip based on ring circulant topologies, Heliyon. 5 (2019) e01516. doi:10.1016/J.HELIYON.2019.E01516.