EM078 » Vector Network Analyzer using SoC FPGA
Vector network analyzers (VNA) are widely used for parameter measurements of active and passive electronic devices and also some properties of materials. VNA is a device, which enable the RF performance, and some other devices to be characterized in terms of network scattering parameters, or S-parameters. Each S-parameter has an amplitude-frequency and phase-frequency characteristics, which are very useful for estimation of device quality. VNA is based on reflectometer: output signal and its reflection from other outputs should be splitted, then some signal processing operations and displaying the result for users. Signal processing is consist of different non-trivial mathematical operations: convolution, the Fourier transform, math operations in complex numbers etc. Another important problem is achievement well-tuning sync between source and sink. Such requirements push us to use SoC FPGA as an optimal platform for realization of handmade VNA.
Vector network analyzers (VNA) designed to measure the characteristics of the signal transmission through the testing device or device under test (DUT), as well as the characteristics of the signal reflection from its ports. Such characteristics called S-parameters. Each of these parameters contains the frequency and phase responses of the DUT in the appropriate direction. The main task of VNA’s is to measure the characteristics of passive and active devices, such as antennas, attenuators, filters, etc. Basic view of devices is shown on figure 1
Figure 1. General view of the device
To measure the S-parameters, the test device receives a sinusoidal signal and measures the signal transmitted through the device and the reflected signal. The measurements repeated for the selected frequency range with the specified increments. The central role in device control block plays DE10-NANO SoC board. It performs real-time signal processing, which includes different non-trivial mathematical operations: convolution, the Fourier transform, root sum squares, trigonometric operations, math operations in complex numbers etc. Another important task is to interface with ADC and DAC and achieve well-tuning synchronization between signal transmitted to and received from the DUT. This part is where FPGA is perfectly suited.
Another task for FPGA is there hard processing system fits great is data post processing and preparation for visualization.
We chose Intel FPGA because it offers a complete solution for the tasks mentioned above. It comes with great educational material, user-friendly software and wide range of architectural capabilities.
VNAs are widely used by electronic engineers for testing their systems. The modern new systems, which are produced by such giants as LeCroy, Rhode&Schwartz, Keysight etc. might be too expensive for small manufactures. The target of our project is to create multipurpose easy-to-use device, which can be available for every enthusiast, who want to analyze his hardware. By adding our project on Github, we can expand the opportunities and create very useful tool together with world-wide community!
The diagram of the prototype of the network vector analyzer shown in the figure 2. The prototype based on the DE10-NANO development board with a connected high speed AD/DA daughter card. Circulator and lock-in amplifier was designed by our team and manufactured on a separate printed circuit board (electric circuit represented in the figures 3 and 4).
Figure 2. Block diagram with peripherals connected to DE10-NANO
First of all, FPGA is best suited for ADC / DAC interface implementation. In our project, we used two approaches – using external chips and using FPGA pins for creation ADC and DAC. It is important to note that our system is expandable and we can add extra ADCs/DACs for creation multiport or even multiple devices testing equipment. FPGA so allows to perform computations in parallel.
FPGA is also best platform to solve problems of synchronization. It is very important when we going to detect the phase difference, for example, between source and reflected signal. Working with S-parameters, we would like to get same values from them: gain, reflection coefficient etc. All these math operations are complicated and asks specific operations (i.e. working with complex numbers), so FPGA is very useful to calculate all values, which can be taken from each S-parameter. In our project, FPGA part works as accelerator of real-time DSP, and it performs tasks such generation of sin wave as a signal transmitted to DUT, evaluation of trigonometric function atan2 and evaluation of root sum squared.
In case of extension the functionality of device FPGA will be useful in computing functions like Fourier transform (moving from the frequency domain representation of the S-parameters to a time domain representation).
We exploit HPS part as a control unit, which realize an interface between user and hardware. HPS allows us to use SD-card controller, USB or Ethernet for data exchanging from/to Development Board. It also well fitted for post processing using DDR3 memory.
Because of it great flexibility, FPGA can quickly adapt to changes during development stage of our VNA. We can convert processing adopting various math for example additional filtering, different calibration methodologies and so on.
We can divide VNA prototype into such functional blocks:
In addition, a calibration kit should always be supplied with vector analyzer.
The program for DE10-NANO consists of FPGA and HPS parts. FPGA part is responsible for interface with ADC and DAC chips, performing data preprocessing and the calculation of the amplitude and phase of the signal. HPS part sets the settings of VNA state machine (frequency, time-out, averaging), initiates every test cycle and prepares the obtained information for visualization on the monitor. The structure of the program shown in the figure 3.
Figure 3. Structure of FPGA design.
Here you can see that for visualization on monitor we used HDMI port on DE10-Nano-SoC.
1. Receiver scheme for acquiring signal from DUT.
Many manufacturers define the characteristics of transmitted through and reflected signals in post-processing, after receiving directly digitized signals. However, high-speed wideband ADCs necessary for that are expensive and difficult to interface with, so they used only in extremely necessary cases. There are also techniques for using analog multipliers or mixers to transfer signals to a low frequency range to achieve availability of usage many expensive ADCs. Unfortunately, we could not get evaluation board with mixer, so we chose the other way – we built analog synchronous detector scheme.
Synchronous detection makes it possible to determine small amplitude signals in conditions of a high noise level . Electronic devices are influenced by flicker noise, which affects the measurements at low frequencies. If the signal is shifted from the low frequency range to the DC level, it is possible to obtain a higher signal-to-noise ratio. Thus, after multiplying the main signal by a local oscillator and measuring the DC voltage level, it is possible to increase the sensitivity of the detection.
A synchronous detector is a linear device; a great advantage of a synchronous detector is the fact that it can be used to determine the active and reactive components. One of the disadvantages of a synchronous detector is the fact that when there is noise near the frequency of the detected signal, a component variable appears that is close to a DC level. This problem was solved by using a low-pass filter of a higher order, and averaging the signal by post-processing methods.
The input of such detector receives the following signals: signal after reflection or passing through the DUT, meander with the frequency and phase of the original signal and meander with the frequency of the original signal, but with a phase of 90 degrees relative to the original signal. Using quick switches and filtering out high frequency at the output of such a detector, we obtain two values: in-phase component and quadrature component. These values are the characteristics of the signal received from DUT, which allows us to calculate the amplitude and phase of the signal by formulas:
Where I stands for in-phase component, Q – quadrature component.
Figure 4. Scheme of Synchronous detector circuit
The created circuit of the synchronous detector realized on operational amplifiers  with a gain switching of +1 and -1 that allows to detect signals from several hertz to several tens of megahertz. This scheme is not the best in terms of low-noise; the main advantages are the simplicity of execution and the cost component of this scheme. The use of multipliers and the generator of sinusoidal signals as a local oscillator contributes to the improvement of the circuit characteristics, such as the signal-to-noise ratio, but is more difficult to implement in the analog domain.
There are various techniques for working with a bidirectional signals presented in system. Since we would like to send some signals in port and receive reflected signal we need such scheme, which allow us to use separated receiver and transmitter and connect them to one port. For example in Gigabit Ethernet, where the signal is distributed in two directions in one serial line, it is near impossible to directly visualize eye diagram of transmitted signal because of reverse traffic. One solution to this problem is a circulator. Depending on the desired frequency range, bill of materials (BOM) for circulator may vary, but the basic principle remains the same: the signal supplied to the first port is presented only on the second port, and the signal coming from the second port is supplied to the third.
Figure 5. Scheme of Circulator
The most popular solution for an electronics engineer is ferrite isolator/circulator, which is common in radio frequency and microwave (even optical fiber) systems, but at frequencies below several hundred megahertz, the size of magnets and ferrites become large and cost of the device is high. For that reason, we used an equivalent circuit of the circulator on operational amplifiers that shows excellent characteristics for reverse isolation and impedance up to frequencies not exceeding 100 MHz.
In our case, circulator has three ports: first is connected to transmitter from de10nano, second is connected to port of DUT and third is connected to receiver. When we send a signal from transmitter, circulator pass it to the second port. After reflection from signal comes back to the second port of circulator, which pass signal to the third port, i.e. to the receiver. All parameters of its elements are depends on which frequency range we are going to work. The example of such circulator is well described in different papers .
3. ADC & DAC implementation
We used THDB ADA daughter card from Terasic (Highspeed AD/DA Card) specifically its digital-to-analog converter for the front-end of VNA test signal generation before its transmission to the DUT port. We exploited DAC at 50 Msps.
We also implemented ADC and DAC without any external IC. We just used FPGA’s pins and a low amount of basic electronic components as resistors and caps. This feature gives ability not to use third party chips and saves space on the board.
However, in practice it is hard to achieve high speed and great ENOB numbers. In our case we achieved SNR = 53 dB with clock frequency 100MHz. Also we unfortunately hadn’t received LTC ADC and DAC evaluation boards so for the project demo we decided to use THDB ADA and on-board ADC .
As about ADC, we choose built-in ADC (in terms of DE10-Nano-SoC), which is Linear Technologies LTC2308. Its sampling rate is somewhat slow (250 ksps for 2-channel mode), but our analog scheme (figure 4) allows us to digitize signal which locates near DC component and so we does not need a speed comparable to DAC.
4. DE10-Nano-SoC board
Top level of project, which is block diagram (bdf) file shown in the figure 6.
Figure 6. Top level block diagram of FPGA design in Quartus II.
Now, let’s look in project functional blocks in more detail:
(a) (b) (c)
Figure 7. (a) – PLLs for system and HDMI clocks and for reset signal generation; (b) – Numerically controlled oscillator (NCO) for creation sin wave signal for transferring to DAC and meander generator for synchronous detector; (c) – Blocks which evaluate phase and frequency responses of signal.
(a) (b) (c)
Figure 8. (a) – Block interfaced two channel ADC; (b) – Programming unit, responsible for the continuous rendering of the HDMI image on the monitor; (c) – State machine performing amplitude and phase measurements at a given frequency.
HPS firmware is a bare metal application and uses hwlib libraries. The processor prepares the frame for display on the monitor, for that we used our own libraries. Processor also controls the operation of the VNA state machine in the FPGA part, which allows us to change the limits and step measurements, holding time, the value of averaging, which makes it possible to implement complex algorithms (such as calibration) without changing the FPGA part.
Working with graphics and various algorithms without a processor would lead to the need of writing complex and voluminous HDL machines, which would increase the development time of the project and would complicate its modification.
Figure 9. QSYS system with HPS
Frequency range of our VNA now is from 1 kHz to 50 MHz with minimum step of 1Hz. Frequency range for visualization can be change.
The hold time on each frequency depends on low-pass filter in the circuit of lock-in amplifier, our implementation requires at least 0.0006 s, but it can be changed due to different components.
Our VNA is designed to test devices with matched load of 100 Ohm.
This VNA measures S11 and S22 parameters.
All project works fine with 50 MHz system clock. FPGA part is not fully used, but since there are many fields of improvements for different DSP tasks, it will be no need to change board for a long time.
Figure 10. Using VNA for testing DUT
Figure 10 shows VNA in run mode.DE10-Nano shows the phase and amplitude characteristics of DUT, which is connected through the circulator. On the X-axis there is a frequency range from 1kHz to 500kHz, on Y-axis on the left there is normalized value of amplitude, drawn with red line; on the Y-axis on the right there is a range of phase - from -90o to 90o, so phase characteristic is drawn with a green line. Full demonstration of VNA run mode can be seen on our video: https://youtu.be/BvW69keXv7Y
DE10-Nano-SoC development board is the brains of the implemented project. The Board implements the following tasks:
Let’s describe functionality of our assembled device. It can be viewed in figure 10.
Figure 11. Assembled VNA prototype
Before the connection of the device under test, a calibration process should be performed. Calibration of a vector network analyzer is an important step in which calibration connectors are connected to the device ports, the results of which determine the set of error coefficients. Generation of sinusoidal signals occurs by command of the user with the help of the NCO IP core, the data from the output of which transferred to the DAC. Parallel to this process, FPGA performs task of formation control meanders. They control switching of analog keys, which can be considered as multiplication of reflected signal with meander. That process effectively creates a DC component and double frequency component. After low pass filtering only DC component which consists valuable information enters ADC. After post processing we display two valuable data (phase and frequency response) on the monitor.
Software used during project development stage:
Project is actively updating on a GitHub.com: em078_vector_analyzer
We created a prototype of a device, which we can greatly expand and upgrade. We can use our project as a platform for develop additional features of VNA, such as:
 Wideband UHF/Microwave Active Isolators: citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.399.5102&rep=rep1&type=pdf
 VNA with another detecting scheme: hforsten.com/cheap-homemade-30-mhz-6-ghz-vector-network-analyzer.html
 Principles of Lock-in Detection: www.youtube.com/watch?v=ZIjBRA2S0NQ
 Lock-in Amplifier: en.wikipedia.org/wiki/Lock-in_amplifier
 Terasic THDB AD/DA Card: www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=278&PartNo=1