EM078 »
Vector Network Analyzer using SoC FPGA
📁Digital Design
👤Philipp Shuklin
 (ITMO University)
📅May 31, 2018
Semifinalist


👀 3135   💬 18

EM078 » Vector Network Analyzer using SoC FPGA

Description

Vector network analyzers (VNA) are widely used for parameter measurements of active and passive electronic devices and also some properties of materials. VNA is a device, which enable the RF performance, and some other devices to be characterized in terms of network scattering parameters, or S-parameters. Each S-parameter has an amplitude-frequency and phase-frequency characteristics, which are very useful for estimation of device quality. VNA is based on reflectometer: output signal and its reflection from other outputs should be splitted, then some signal processing operations and displaying the result for users. Signal processing is consist of different non-trivial mathematical operations: convolution, the Fourier transform, math operations in complex numbers etc. Another important problem is achievement well-tuning sync between source and sink. Such requirements push us to use SoC FPGA as an optimal platform for realization of handmade VNA.

Demo Video

  • URL: https://www.youtube.com/watch?v=BvW69keXv7Y

  • Project Proposal

    1. High-level Project Description

    Vector network analyzers (VNA) designed to measure the characteristics of the signal transmission through the testing device or device under test (DUT), as well as the characteristics of the signal reflection from its ports. Such characteristics called S-parameters. Each of these parameters contains the frequency and phase responses of the DUT in the appropriate direction. The main task of VNA’s is to measure the characteristics of passive and active devices, such as antennas, attenuators, filters, etc. Basic view of devices is shown on figure 1

    Figure 1. General view of the device

    To measure the S-parameters, the test device receives a sinusoidal signal and measures the signal transmitted through the device and the reflected signal. The measurements repeated for the selected frequency range with the specified increments. The central role in device control block plays DE10-NANO SoC board. It performs real-time signal processing, which includes different non-trivial mathematical operations: convolution, the Fourier transform, root sum squares, trigonometric operations, math operations in complex numbers etc. Another important task is to interface with ADC and DAC and achieve well-tuning synchronization between signal transmitted to and received from the DUT. This part is where FPGA is perfectly suited.

    Another task for FPGA is there hard processing system fits great is data post processing and preparation for visualization.

    We chose Intel FPGA because it offers a complete solution for the tasks mentioned above. It comes with great educational material, user-friendly software and wide range of architectural capabilities.

    Target users:

    VNAs are widely used by electronic engineers for testing their systems. The modern new systems, which are produced by such giants as LeCroy, Rhode&Schwartz, Keysight etc. might be too expensive for small manufactures. The target of our project is to create multipurpose easy-to-use device, which can be available for every enthusiast, who want to analyze his hardware. By adding our project on Github, we can expand the opportunities and create very useful tool together with world-wide community!

    2. Block Diagram

    The diagram of the prototype of the network vector analyzer shown in the figure 2. The prototype based on the DE10-NANO development board with a connected high speed AD/DA daughter card. Circulator and lock-in amplifier was designed by our team and manufactured on a separate printed circuit board (electric circuit represented in the figures 3 and 4).

    Figure 2. Block diagram with peripherals connected to DE10-NANO

    3. Intel FPGA Virtues in Your Project

    First of all, FPGA is best suited for ADC / DAC interface implementation. In our project, we used two approaches – using external chips and using FPGA pins for creation ADC and DAC. It is important to note that our system is expandable and we can add extra ADCs/DACs for creation multiport or even multiple devices testing equipment. FPGA so allows to perform computations in parallel.

    FPGA is also best platform to solve problems of synchronization. It is very important when we going to detect the phase difference, for example, between source and reflected signal. Working with S-parameters, we would like to get same values from them: gain, reflection coefficient etc. All these math operations are complicated and asks specific operations (i.e. working with complex numbers), so FPGA is very useful to calculate all values, which can be taken from each S-parameter. In our project, FPGA part works as accelerator of real-time DSP, and it performs tasks such generation of sin wave as a signal transmitted to DUT, evaluation of trigonometric function atan2 and evaluation of root sum squared.

    In case of extension the functionality of device FPGA will be useful in computing functions like Fourier transform (moving from the frequency domain representation of the S-parameters to a time domain representation).

    We exploit HPS part as a control unit, which realize an interface between user and hardware. HPS allows us to use SD-card controller, USB or Ethernet for data exchanging from/to Development Board. It also well fitted for post processing using DDR3 memory.

    Because of it great flexibility, FPGA can quickly adapt to changes during development stage of our VNA. We can convert processing adopting various math for example additional filtering, different calibration methodologies and so on.

    4. Design Introduction

    We can divide VNA prototype into such functional blocks:

    • Receiver scheme for acquiring signal from DUT,
    • Circulator,
    • DAC Board,
    • DE10-Nano-SoC Board.

    In addition, a calibration kit should always be supplied with vector analyzer.

    The program for DE10-NANO consists of FPGA and HPS parts. FPGA part is responsible for interface with ADC and DAC chips, performing data preprocessing and the calculation of the amplitude and phase of the signal. HPS part sets the settings of VNA state machine (frequency, time-out, averaging), initiates every test cycle and prepares the obtained information for visualization on the monitor. The structure of the program shown in the figure 3.

    Figure 3. Structure of FPGA design.

    Here you can see that for visualization on monitor we used HDMI port on DE10-Nano-SoC.

    5. Function Description

    1. Receiver scheme for acquiring signal from DUT.

    Many manufacturers define the characteristics of transmitted through and reflected signals in post-processing, after receiving directly digitized signals. However, high-speed wideband ADCs necessary for that are expensive and difficult to interface with, so they used only in extremely necessary cases. There are also techniques for using analog multipliers or mixers to transfer signals to a low frequency range to achieve availability of usage many expensive ADCs. Unfortunately, we could not get evaluation board with mixer, so we chose the other way – we built analog synchronous detector scheme.

    Synchronous detection makes it possible to determine small amplitude signals in conditions of a high noise level [3]. Electronic devices are influenced by flicker noise, which affects the measurements at low frequencies. If the signal is shifted from the low frequency range to the DC level, it is possible to obtain a higher signal-to-noise ratio. Thus, after multiplying the main signal by a local oscillator and measuring the DC voltage level, it is possible to increase the sensitivity of the detection.

     A synchronous detector is a linear device; a great advantage of a synchronous detector is the fact that it can be used to determine the active and reactive components. One of the disadvantages of a synchronous detector is the fact that when there is noise near the frequency of the detected signal, a component variable appears that is close to a DC level. This problem was solved by using a low-pass filter of a higher order, and averaging the signal by post-processing methods.

    The input of such detector receives the following signals: signal after reflection or passing through the DUT, meander with the frequency and phase of the original signal and meander with the frequency of the original signal, but with a phase of 90 degrees relative to the original signal. Using quick switches and filtering out high frequency at the output of such a detector, we obtain two values: in-phase component and quadrature component. These values are the characteristics of the signal received from DUT, which allows us to calculate the amplitude and phase of the signal by formulas:

    Where I stands for in-phase component, Q – quadrature component.

    Figure 4. Scheme of Synchronous detector circuit

    The created circuit of the synchronous detector realized on operational amplifiers [4] with a gain switching of +1 and -1 that allows to detect signals from several hertz to several tens of megahertz. This scheme is not the best in terms of low-noise; the main advantages are the simplicity of execution and the cost component of this scheme. The use of multipliers and the generator of sinusoidal signals as a local oscillator contributes to the improvement of the circuit characteristics, such as the signal-to-noise ratio, but is more difficult to implement in the analog domain.

    2. Circulator.

    There are various techniques for working with a bidirectional signals presented in system. Since we would like to send some signals in port and receive reflected signal we need such scheme, which allow us to use separated receiver and transmitter and connect them to one port. For example in Gigabit Ethernet, where the signal is distributed in two directions in one serial line, it is near impossible to directly visualize eye diagram of transmitted signal because of reverse traffic. One solution to this problem is a circulator. Depending on the desired frequency range, bill of materials (BOM) for circulator may vary, but the basic principle remains the same: the signal supplied to the first port is presented only on the second port, and the signal coming from the second port is supplied to the third.

    Figure 5. Scheme of Circulator

    The most popular solution for an electronics engineer is ferrite isolator/circulator, which is common in radio frequency and microwave (even optical fiber) systems, but at frequencies below several hundred megahertz, the size of magnets and ferrites become large and cost of the device is high. For that reason, we used an equivalent circuit of the circulator on operational amplifiers that shows excellent characteristics for reverse isolation and impedance up to frequencies not exceeding 100 MHz.

    In our case, circulator has three ports: first is connected to transmitter from de10nano, second is connected to port of DUT and third is connected to receiver. When we send a signal from transmitter, circulator pass it to the second port. After reflection from signal comes back to the second port of circulator, which pass signal to the third port, i.e. to the receiver. All parameters of its elements are depends on which frequency range we are going to work. The example of such circulator is well described in different papers [1].

    3. ADC & DAC implementation

    We used THDB ADA daughter card from Terasic (Highspeed AD/DA Card) specifically its digital-to-analog converter for the front-end of VNA test signal generation before its transmission to the DUT port. We exploited DAC at 50 Msps.

    We also implemented ADC and DAC without any external IC. We just used FPGA’s pins and a low amount of basic electronic components as resistors and caps. This feature gives ability not to use third party chips and saves space on the board.

    However, in practice it is hard to achieve high speed and great ENOB numbers. In our case we achieved SNR = 53 dB with clock frequency 100MHz. Also we unfortunately hadn’t received LTC ADC and DAC evaluation boards so for the project demo we decided to use THDB ADA and on-board ADC [5].

    As about ADC, we choose built-in ADC (in terms of DE10-Nano-SoC), which is Linear Technologies LTC2308. Its sampling rate is somewhat slow (250 ksps for 2-channel mode), but our analog scheme (figure 4) allows us to digitize signal which locates near DC component and so we does not need a speed comparable to DAC.

    4. DE10-Nano-SoC board

    Top level of project, which is block diagram (bdf) file shown in the figure 6.

    Figure 6. Top level block diagram of FPGA design in Quartus II.

    Now, let’s look in project functional blocks in more detail:

                                     (a)                                                             (b)                                                            (c)

    Figure 7. (a) – PLLs for system and HDMI clocks and for reset signal generation; (b) – Numerically controlled oscillator (NCO) for creation sin wave signal for transferring to DAC and meander generator for synchronous detector; (c) – Blocks which evaluate phase and frequency responses of signal.

                                 (a)                                                             (b)                                                            (c)

    Figure 8. (a) – Block interfaced two channel ADC; (b) – Programming unit, responsible for the continuous rendering of the HDMI image on the monitor; (c) – State machine performing amplitude and phase measurements at a given frequency.

    HPS firmware is a bare metal application and uses hwlib libraries. The processor prepares the frame for display on the monitor, for that we used our own libraries. Processor also controls the operation of the VNA state machine in the FPGA part, which allows us to change the limits and step measurements, holding time, the value of averaging, which makes it possible to implement complex algorithms (such as calibration) without changing the FPGA part.

    Working with graphics and various algorithms without a processor would lead to the need of writing complex and voluminous HDL machines, which would increase the development time of the project and would complicate its modification.

    Figure 9. QSYS system with HPS

    6. Performance Parameters

    Frequency range of our VNA now is from 1 kHz to 50 MHz with minimum step of 1Hz. Frequency range for visualization can be change.
    The hold time on each frequency depends on low-pass filter in the circuit of lock-in amplifier, our implementation requires at least 0.0006 s, but it can be changed due to different components.

    Our VNA is designed to test devices with matched load of 100 Ohm.

    This VNA measures S11 and S22 parameters.

    All project works fine with 50 MHz system clock. FPGA part is not fully used, but since there are many fields of improvements for different DSP tasks, it will be no need to change board for a long time.

    VNA test

    Figure 10. Using VNA for testing DUT

    Figure 10 shows VNA in run mode.DE10-Nano shows the phase and amplitude characteristics of DUT, which is connected through the circulator. On the X-axis there is a frequency range from 1kHz to 500kHz, on Y-axis on the left there is normalized value of amplitude, drawn with red line; on the Y-axis on the right there is a range of phase - from -90o to 90o, so phase characteristic is drawn with a green line. Full demonstration of VNA run mode can be seen on our video: https://youtu.be/BvW69keXv7Y

     

    7. Design Architecture

    DE10-Nano-SoC development board is the brains of the implemented project. The Board implements the following tasks:

    • Generation of sinusoidal signals in the specified range (FPGA)
    • Acquisition of reflected / transmitted signals (FPGA)
    • Data processing, frequency response and phase response (FPGA, Cortex A9)
    • Display the measurement information on the monitor connected to board via HDMI (Cortex A9, FPGA)
    • Calibration of the device

    Let’s describe functionality of our assembled device. It can be viewed in figure 10.

    Figure 11. Assembled VNA prototype

    Before the connection of the device under test, a calibration process should be performed. Calibration of a vector network analyzer is an important step in which calibration connectors are connected to the device ports, the results of which determine the set of error coefficients. Generation of sinusoidal signals occurs by command of the user with the help of the NCO IP core, the data from the output of which transferred to the DAC. Parallel to this process, FPGA performs task of formation control meanders. They control switching of analog keys, which can be considered as multiplication of reflected signal with meander. That process effectively creates a DC component and double frequency component. After low pass filtering only DC component which consists valuable information enters ADC. After post processing we display two valuable data (phase and frequency response) on the monitor.

    Software used during project development stage:

    • The development of the electrical circuit carried out using LTSpice software.
    • FPGA project was created using Quartus IDE II 16.0.
    • Software part of SoC project design carried out with SoC EDS 16.0 and ARM DS-5.

    Project is actively updating on a GitHub.com: em078_vector_analyzer


     

    Future plans.

    We created a prototype of a device, which we can greatly expand and upgrade. We can use our project as a platform for develop additional features of VNA, such as:

    • Adding calibration functionality to prevent our analog schemes add errors in measurements
    • Implementing new channel so we can measure more parameters and create full s-parameters matrix for two-ports devices
    • We can add Fourier transform for moving from the frequency domain representation of the S-parameters to a time domain representation. It can be very helpful for analyzing the nature of DUT because of it representability.
    • We can select ADC and DAC with higher specs (speed, ENOB, etc) and use more bits in FPGA processing to raise characteristics of our device. For that, we likely will utilize high-speed transceivers, which are presented in Intel FPGA. Also we can use FPGA pins as ADCs and DACs for creation ultra-compact version of device.
    • Add more abilities into interface so users can have more options: change frequency range, autoscale/manual scale on axes, save the data for future analysis on a PC and other items.

    References:

    [1] Wideband UHF/Microwave Active Isolators: citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.399.5102&rep=rep1&type=pdf

    [2] VNA with another detecting scheme: hforsten.com/cheap-homemade-30-mhz-6-ghz-vector-network-analyzer.html

    [3] Principles of Lock-in Detection: www.youtube.com/watch?v=ZIjBRA2S0NQ

    [4] Lock-in Amplifier: en.wikipedia.org/wiki/Lock-in_amplifier

    [5] Terasic THDB AD/DA Card: www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=278&PartNo=1



    18 Comments

    Pedro Miguel Baptista Machado · Judge ★
    Interesting project and the result was a helpful framework. More details about the functional simulation should be provided. Results, discussion and future work and references sections should be included.
    🕒 May 28, 2018 11:15 AM
    EM078🗸
    Dear Mr. Machado,
    Thank you for your comment. We decided that readers would be more interested in final implementation than in functional simulation of a design. However, we have analog schemes models, created with LTSpice, so every user can check not only program part of our project, but also the scheme implementation. Could you please specify what functional simulation aspects should we present?
    The Future work part is included in part 6 of our project description. We added references at the end of this document.
    🕒 May 30, 2018 05:23 PM
    Pedro Miguel Baptista Machado · Judge ★
    Dear team, are you really sure about what you wrote: "We decided that readers would be more interested in final implementation than in functional simulation of a design."? Shouldn't you accept readers/judges feedback as instead of making wrong assumptions? The main problem with your work is the reading flow. The information is sparsed and makes it very difficult to read the document.
    I expect to see the ModelSim simulation of the circulator provides more detailed information. Please mind that ModelSim is a tool that comes with IntelQuartus. The Future work should come last (before the references) otherwise it disrupts the reading flow.
    There is little information about the results. You have to provide evidence that your system is working as described. ModelSim simulation and SignalTap II are tools that you can use to provide evidence that your system works as described.
    Kind Regards,
    Pedro
    🕒 May 30, 2018 05:53 PM
    EM078🗸
    Dear Mr. Machado,
    Thank you for your comment. By we decided we mean, that when we were filling all parts of the form we decicded to make an accent on a whole implementation, skipping the testing part. It looks like a misunderstanding in terms.
    We corrected the order in the text for better reading flow, nevertheless, all seven blocks of text has it's own target with it's descrition and we just filled it. We have also our own document, which has better structure, which can be downloaded (the link added)
    As for simulation: ModelSim provides to create simulations of digital logic schemes while circulator and synchronous detector is analog circuits. The main evidence of our project works is presented on video, but in case if it is not avaliable we also added a photoproof of it.
    Best regards,
    EM078 Team
    🕒 May 31, 2018 10:56 AM
    Pedro Miguel Baptista Machado · Judge ★
    Well done. Apologies because the document that I was referring is the online document above. I did not ask to create a google doc document. Also, I meant to say do a functional simulation of the VNA state machine and not the circulator. The document (above) reading flow is much better now.
    Kind regards,
    Pedro
    🕒 May 31, 2018 11:02 AM
    EM078🗸
    Dear Mr. Machado,
    The total state machine is implemented in HPS part (send signal, wait for response, take data from ADC, filter it etc.), so it cannot be shown on Modelsim. We are upset if our project looks like it doesn't work, because we already used our device for different measurements for specific task.
    🕒 May 31, 2018 11:18 AM
    Pedro Miguel Baptista Machado · Judge ★
    Can you please clarify what is implemented on the HPS and on the FPGA side?
    🕒 May 31, 2018 11:35 AM
    EM078🗸
    HPS creates sweep mode of sine waves, receive data from ADC, creates image for display, download it to shared with FPGA memory
    The so-called "vna state machine" is created to get slow changing data from HPS to FPGA and from FPGA to HPS (i.e. ADC data, mean window etc)
    FPGA generate sine with frequency, reads ADC data, calculate amplitude and phase, create videostream on HDMI, receive info from switches and pushbuttons.
    🕒 May 31, 2018 11:48 AM
    EM078🗸
    Our protect is available on GitHub, we are glad to explain each part of our project including analogue circuits
    🕒 May 31, 2018 11:52 AM
    Donald Bailey · Judge ★
    An interesting and useful application of SoC FPGA. How do you propose to split the parameter computation between the FPGA and HPS?
    The content of the proposed custom board is also light. What do you mean by "custom circulators"
    🕒 Jan 25, 2018 08:43 PM
    EM078🗸
    Dear Mr. Bailey, Thank you for you questions!
    1. FPGA part should work as accelerator of real-time DSP, its aim is mostly to transform signals from time domain to frequency domain, also FPGA will be useful in computing functions like Fourier transform (moving from the frequency domain representation of the S-parameters to a time domain representation); FPGA also should be used as signal generator for VNA to work in different modes; FPGA will also detect phase and amplitude changes between source signal and received passed and reflected signals. HPS part would be used as a control unit, which would realize an interface between user and hardware. HPS allows us to use SD-card controller, USB or Ethernet for data exchanging from/to Development Board. It also should be well fitted for postprocessing using DDR3 memory. For example, an eye diagram can be synthesized from S-parameter using postprocessing.
    2. As for custom circulators - since we would like to send some signals in port and receive reflected signal we need such scheme, which allow us to use seprated receiver and transmitter and connect them to one port. The circullator is a scheme, which works like optical circullator. It has (in our case) 3 ports: first is connected to transmitter from de10nano, second is connected to port of device and third connected to receiver. When we send a signal from transmitter circullator pass it to the second port. After reflection from signal comes back to the second port of circullator, which pass signal to the third port, i.e. to the receiver. All parameters of it's elements are depends on which frequency range we are going to work. The example of such circullator is well described in different papers (i.e. http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.399.5102&rep=rep1&type=pdf), but the main operation is to pick up correct elements and after that to calibrate it.
    The most popular solution for an electronics engineer is ferrite isolator/circulator, which is common in radio frequency and microwave (even optical-fiber) systems but it is not available for ultra-high frequency and extremely wide bandwidths. For this reason we used an equivalent circuit of the circulator on operational amplifiers, that shows excellent characteristics for reverse isolation and impedance up to frequencies not exceeding 100 MHz.
    🕒 Jan 29, 2018 05:35 PM
    Bing Xia · Judge ★
    Work hard and going well.
    🕒 Jan 19, 2018 06:13 AM
    EM078🗸
    Thank you!
    🕒 Jan 20, 2018 11:17 AM
    berkay egerci
    keep going! good project and good luck !
    🕒 Jan 14, 2018 09:14 PM
    berkay egerci
    keep going! good project and good luck !
    🕒 Jan 13, 2018 09:57 AM
    kemal eddin ahmedzad
    keep going ! i voted
    🕒 Jan 12, 2018 01:15 PM
    MOHAMED
    Good Project. Keep moving.
    🕒 Jan 12, 2018 02:26 AM