Rules

Items for Submission

All submitted projects should be based on, and make complete use of the FPGA on the Cloud Connectivity Kit. Teams will be rewarded for full use of the contest platforms, including products from Microsoft and Analog Devices.

  1. Technical Proposal (due by Sept. 30, 2021) includes:
    • High-level project introduction and performance expectation
    • Block diagram
    • Expected sustainability results, projected resource savings
  2. Technical paper (due by Feb 7, 2022) includes:
    • High-level project introduction and performance expectation (latest version)
    • Block diagram (latest version)
    • Describe the FPGA virtues demonstrated by your project
      • Boosts performance
      • Expands I/O
      • Adapts to changes
    • Functional description and implementation
    • Performance metrics, performance to expectation
    • Sustainability results, resource savings achieved
    • Conclusion
  3. Demonstration (due by Feb 7, 2022) includes:
    • Video demonstration of your design. (maximum length: 10 minutes). Uploaded to a publicly accessible site and share the link in your technical paper.
    • Description of theory, function, and performance of your design
  4. Project source code (due by Feb 7, 2022):
    • Teams who progress to the Regional Finals are required to upload all project source code, and confidentially share the project link to the contest organizers for reference by the judges.

Judging Criteria

  1. Design Concept: 30%
    • Creativity: 10%
    • Functionality: 10%
    • Sustainability impact of the concept: 10%
  2. Design Implementation: 35%
    • Demonstration of FPGA virtues: 15%
    • Solution submission must use content platforms including Analog Devices plug-in boards, Azure IoT Central or Azure IoT Hub: 20%
  3. Design Performance: 35%
    • Demonstrated technical performance versus performance expectations: 10%
    • Sustainability results, significant resource savings achieved: 10%
    • Completeness. Optimization of hardware, software, and appearance: 20%

Contest Rules

  • The InnovateFPGA Design Contest complies with US Federal Gaming Laws. Contest partners including Microsoft, Analog Devices, Inc., Intel Corporation, Arrow Electronics Inc., Macnica Inc., Mouser Electronics, Inc., and Digikey Electronics are not liable for compliance with US Federal Gaming Laws or the execution and administration of the game.
  • All papers should be submitted in English. Teams from Greater China region can compete in Chinese until the Grand Final, which has to be in English.
  • Teams can be no larger than 3 members.
  • All entrants must be at least 18 years of age.
  • Individuals can only be a member of one team.
  • Students can be supervised by a teacher or professor.
  • All entries must be submitted before the stated deadline. Unfortunately, requests for extensions or late submissions cannot be accepted.
  • If a member of the team needs to be replaced for any reason, the team must apply for approval from the organizers.
  • Existing designs may be submitted, but they cannot have been submitted in a previous contest of any kind, and they must not have been sold in any form. Judges reserve the right to exclude entrants whose projects appear to be commercial products, previously entered into other contests, or derivative of prior contest entries.
  • Each design must be entirely created by the participants submitting it based on the contest resources provided. Designs containing open source work must clearly cite ownership and/or authorship. Designs containing third party IP must demonstrate permission for its use.
  • You may make changes or enhancements to your design at any time up to the judging date. Only the most recent version of your proposal, design, or video will remain on the InnovateFPGA site and be considered by the judges.
  • By entering the competition, you allow Terasic and InnovateFPGA partners to use your project information and associated content for marketing purposes.
  • Teams must not include Terasic or contest sponsor logos in their designs, or imply Terasic or contest partners have endorsed it in any way.