Deadline to register is Jun 15, 2019.
Teams can still edit your proposals during judging period.

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📁Digital Design
👤Mogana Priya Palanisamy (Sri Krishna college of Technology)
📅Mar 21, 2019
Designing of Low power approximate adders using Modified SARA technique in 90nm technology.
In our project, the proposed adder is designed and tested for low power, delay and area using SARA with only MUX, SARA with Decoder and SARA with only NAND. The adder designed using SARA with only NAND is found to exhibit low power and delay with same area. All the adders were simulated and synthesized using Verilog and Cadence tool and their power, delay and power delay products were compared. Our project aims at proposing low power accuracy adder for multiplier applications. When power is considered SARA using Mux is 45% better than SARA using Decoder. Existing SARA is 14% better than SARA using Mux. Modified SARA is 1.13% better than existing SARA. When area is considered: SARA design using Mux is 38% better than SARA design using Decoder. Existing SARA design is 15% better than SARA design using Mux. There is no difference of area in existing SARA design and SARA design using only NAND gates. In terms of Delay: Modified SARA is 27% better than Existing SARA.
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📁Machine Learning
👤Abarajithan Gnaneswaran (University of Moratuwa)
📅Apr 16, 2019
Traffic signals generally are controlled by preset timers. This makes the timing blind to dynamic changes in traffic. We build a vision based traffic-level sensing system that is robust to (day, night, twilight) and weather conditions (rain..etc) and lighting conditions, by implementing a CNN on an FPGA.

The traffic level sensed will be shared to the multiple devices placed around the intersection, the levels of each lane will be compared and the extra time (delta t) will be calculated to be added to the static timing.

This method combines the stability of static timing and the robustness of vision based timing.
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