👤Mogana Priya Palanisamy
(Sri Krishna college of Technology)
📅Mar 21, 2019
Designing of Low power approximate adders using Modified SARA technique in 90nm technology.
In our project, the proposed adder is designed and tested for low power, delay and area using SARA with only MUX, SARA with Decoder and SARA with only NAND. The adder designed using SARA with only NAND is found to exhibit low power and delay with same area. All the adders were simulated and synthesized using Verilog and Cadence tool and their power, delay and power delay products were compared. Our project aims at proposing low power accuracy adder for multiplier applications. When power is considered SARA using Mux is 45% better than SARA using Decoder. Existing SARA is 14% better than SARA using Mux. Modified SARA is 1.13% better than existing SARA. When area is considered: SARA design using Mux is 38% better than SARA design using Decoder. Existing SARA design is 15% better than SARA design using Mux. There is no difference of area in existing SARA design and SARA design using only NAND gates. In terms of Delay: Modified SARA is 27% better than Existing SARA.
(University of Moratuwa)
📅Apr 16, 2019
Traffic signals generally are controlled by preset timers. This makes the timing blind to dynamic changes in traffic. We build a vision based traffic-level sensing system that is robust to (day, night, twilight) and weather conditions (rain..etc) and lighting conditions, by implementing a CNN on an FPGA.
The traffic level sensed will be shared to the multiple devices placed around the intersection, the levels of each lane will be compared and the extra time (delta t) will be calculated to be added to the static timing.
This method combines the stability of static timing and the robustness of vision based timing.
(Lideta Catholic Cathdral School)
📅May 11, 2019
AI is growing in a rapid way, this could be implemented in many fields and our goal is to use AI in the medical field. Here in Ethiopia many people die because of lack of medicine and other things in time, our idea is that we can use the AI machine to help. For example, we can use it to guess the disease in which one is infected from the symptoms. Through time we could improve this and take it to the higher level and make it helpful.
(University of Auckland)
📅Jun 07, 2019
With the explosive interest in the utilization of Neural Networks (NN), several approaches have taken place to make them faster, more accurate or power efficient; one technique used to simplify inference models is the utilization of binary representations for weights, activations, inputs and/or outputs. This competition entry will present a novel approach to train from scratch Binary Neural Networks (BNN) using neuroevolution as its base technique (gradient descent free) executed on Intel FPGA platforms to achieve better results than general purpose GPUs
Traditional NN uses different variants of gradient descent to train fixed topologies, as an extension to that optimization technique, BNN research has focused on the application of such algorithms to discrete environments, with weights and/or activations represented by binary values (-1,1). It has been identified by the authors that the most frequent obstacle of the approach taken by multiple BNN publications to date is the utilization of gradient descent, given that the procedure was originally designed to deal with continuous values, not with discrete spaces. Even when it has been shown that precision reduction (Float32 -> Float16 -> Int16) can train NN at a comparable precision , the problem resides in the adaptation of a method originally designed for continuous contexts into a different set of values that create instabilities at time of training.
In order to tackle that problem, it is imperative to take a completely different approach to how BNNs are trained, which is the main proposition of this project, in which we expose a new methodology to obtain neural networks that use binary values in weights, activations, operations and is completely gradient free; which brings us to the brief summary of the capabilities of this implementation:
• Use weights and activations as unsigned short int values (16 bits)
• Use only logic operations (AND, XOR, OR...), no need of Arithmetic Logic Units (ALU)
• Calculate distance between individuals with hamming distance
• Use evolutionary algorithms to drive the space search and network topology updates.
These substantial changes simplify the computing architecture needed to execute the algorithm, which match natively with the Logic Units in the FPGA, but also allows us to design processing elements that effectively adapt to the problem to be solved, while at the same time, remain power efficient in terms of the units needed to deploy because agents with un-optimized structures would automatically be disregarded.
The algorithm proposed, Binary SUNA (SUNA  with binary extensions ), will be used to solve standard reinforcement learning challenges, which are going to be connected to an FPGA to solve them more efficiently, given that the architecture will match the evolved network at multiple stages, specially during training and inference. Comparison of the performance gains between CPU, GPU and FPGA will be demonstrated.
 Michaela Blott et al. 2018. FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. ACM Trans. Reconfigurable Technology
 Danilo Vargas et al. 2017. Spectrum-Diverse Neuroevolution With Unified Neural Models. IEEE Transactions on Neural Networks and Learning Systems 28
(Now Why Would You Do That)
📅May 26, 2019
This project intends to create a working prototype of an add-on solution for motor vehicles (including motor cycles) to actively detect pedestrian movements and warn of potential collision hazards.
The solution will project information onto a heads-up display to minimise distraction to the driver.
(Rajlee electronics and innovation (opc)Pvt ltd)
📅May 21, 2019
Machine Learning Mechanism
we are using force learning with specific mechanism procedure to find the best optimization results. Like in Convex Optimization we require a lot of od procedure to find an optimum solution.
if our daily like we see lots of type of problems. like in 5G cellular Network we are using MIMO-OFDM which has the main demerit as PAPR. using MLM technique we can resolve it in real-time as we at best efficient till now ever solution has bee found.
📅May 22, 2019
Effect of Diabetes on the eye is known as Diabetic Retinopathy which may lead to blindness in its furthermost stage. Highly skilled Doctors or Ophthalmologists use to inspect the patient's eye to detect the affectedness of this disease. But the amount of well-trained doctors is very less compare to drastically increasing amounts of patients. So proper treatment is nearly impossible. Plus also founding doctors in the remote locations is rarely possible. This Diabetic Retinopathy comes with no early symptoms. Only regular eye-checking need to be done to diagnosis it's starting affectedness. So we have planned to make an engineering-based solution making a standalone system which will do the primary diagnosis of the eye & suggest the patient the immediate precaution they need to take.
(RIEIT Punjab-144533, India)
📅May 25, 2019
On road driver’s fatigue and drowsiness is contributing more than 30% of reported road accidents. Driver drowsiness can be estimated by monitoring biomedical signals, visual assessment of driver’s bio-behavior from face images, by monitoring drivers performance or by combines all the above techniques. The proposed algorithm is based on live monitoring of EAR (Eye aspect Ratio) by application of Image processing. HD live video is decomposed in continues frames and facial landmarks have been detected using pre-trained Neural Network based Dlib functions. Dlib functions are trained using HAAR Cascade algorithm. Intel’s Open source Image processing libraries (OPEN CV) is used as a primary Image processing tool. EAR is calculated by calculating Euclidean distance between measured eye coordinates. Blink and microsleep detection mechanism are implemented by monitoring the EAR against a threshold value. Blinks and drowsiness level are displayed on a monitor screen with microsleep detection audio warning.
In this contest, we are proposing the compact, efficient and standalone FPGA based hardware implementation of our research work published as:
📁Internet of Things
(st . Josephs college , Bharathidasan university )
📅May 30, 2019
The rapid growth of technology has made our lives easier. There is a phenomenal growth in the automobile sector nowadays. It has created a substantial demand for auto service station, where the customer may not get vehicle information about the status of the vehicle service and the correct duration of the delivery. This problem is rectified by using the proposed system. The Industrial Internet of Things (IIoT) and FPGA facilitate Analytics present opportunities to make processing consequently, more safety. There is a wide range of IIoT-related technologies applicable at different satiation. In this system, the camera captures the image of number plate of the vehicle and tracks the different levels of the services, processing and tracing the number plate by using image processing. FGPA system sends the vehicle information to authority of the service station and also updates the section information to computer and customer mobile App.
👤Lee Yee Ann
(Universiti Malaysia Perlis (UniMAP))
📅Jun 09, 2019
The hybrid multilayered perceptron (HMLP) is a type of artificial neural network (ANN) that was introduced as an enhancement to the multilayered perceptron (MLP). At the same time, modified recursive prediction error (MRPE) training algorithm was introduced together with the HMLP to train the HMLP. The HMLP is comprised of many simple processing nodes that operate independently from other nodes makes the HMLP a concurrent system; whereas the outlined steps and the equations used by the MRPE makes the MRPE a sequential system.
In order to implement both HMLP and MRPE on the same device, a device that can combine both concurrent and sequential system is the best option. The Cyclone V SoC FPGA onboard the DE10-Nano that has a FPGA and a SoC within the same device is a suitable candidate. The concurrent HMLP can be implemented on the FPGA, and the MRPE can be executed on the SoC of the target SoC FPGA device.
In order to achieve the goal of implementing the HMLP and the MRPE on SoC FPGA, a concurrent FPGA-based architecture is to be developed for implementing the HMLP on the FPGA, an interface module is to be developed for interfacing the HMLP module on FPGA with the SoC, and a MRPE program to execute the MRPE training algorithm on SoC is to be developed.
(Tokyo Institute of Technology)
📅Jun 13, 2019
This project presents an accurate, fast, and energy-efficient object detector with a thermal camera on an FPGA. A thermal camera outputs pixel values which represent heat (temperature), and the output is gray-scale images. Since the thermal cameras do not depend on whether there is the light or not unlike other visible range cameras, object detection using the thermal camera is reliable without ambient surrounding. Additionally, for a surveillance system, visible images are not suitable since they potentially violates user privacy. Thus, this topic is of a broad interest in object surveillance and action recognition. However, since it is challenging to extract informative features from the thermal images, the implementation challenges of the object detector with high accuracy remain. In recent works, convolutional neural networks (CNNs) outperform conventional techniques, and a variety of object detectors based on the CNNs have been proposed. The representative networks are single-shot detectors that consist of a CNN and infer locations and classes simultaneously (e.g., SSD and YOLOv2). Although the primary advantage of the type is that it enables to train detection and classification simultaneously, the resulting increased computation time and area requirements can cause problems of implementation on an FPGA. Also, as for the proposed networks on RGB three channel images, one of the problems is false positive; the realization of a more reliable object detector is required. This project investigates an FPGA implementation of a such reliable YOLOv2-based object detector that meets high accuracy and real-time processing requirements. Well-known model compression techniques, both a quantization and a weight pruning are applied to our model without significant accuracy degradation, and thereby the model meets the requirements mentioned above.
(Siddartha Inst of tech)
📅Jun 14, 2019
The main motive of this project is to detect if the driver is drunk or not using FPGA.